Publications on Design Flow and Methodology

[1] I. Sander, A. Jantsch, and S.-H. Attarzadeh-Niaki. ForSyDe: System design using a functional language and models of computation. In S. Ha and J. Teich, editors, Handbook of Hardware/Software Codesign, pages 99--140. Springer Netherlands, 2017. [ bib ]
design flow, modeling
[2] S.-H. Attarzadeh-Niaki, E. Altinel, M. Koedam, A. Molnos, I. Sander, and K. Goossens. A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications, pages 157--174. Springer International Publishing, Cham, 2017. [ bib | DOI | http ]
design flow
[3] P. Diallo, S.-H. Attarzadeh-Niaki, F. Robino, I. Sander, J. Champeau, and J. Ã–berg. A formal, model-driven design flow for system simulation and multi-core implementation. In Symposium on Industrial Embedded Systems (SIES), Siegen, Germany, June 2015. [ bib | DOI ]
design flow
[4] S. H. Attarzadeh Niaki, M. Mikulcak, and I. Sander. Rapid virtual prototyping of real-time systems using predictable platform characterizations. In Forum on Specification and Design Languages (FDL 2013), Paris, France, Sept. 2013. [ bib ]
design flow, simulation
[5] S. H. Attarzadeh Niaki and I. Sander. An automated parallel simulation flow for heterogeneous embedded systems. In Proceedings of Design Automation and Test in Europe (DATE '13), pages 27--30, Grenoble, France, March 2013. [ bib ]
design flow, simulation
[6] G. Ungureanu. Automatic software synthesis from high-level forsyde models targeting massively parallel processors. Master's thesis, KTH, School of Information and Communication Technology (ICT), 2013. [ bib ]
design flow, synthesis
[7] M. Mikulcak. Development of a predictable hardware architecture template and integration into an automated system design flow. Master's thesis, KTH, School of Information and Communication Technology (ICT), 2013. [ bib ]
design flow, synthesis
[8] E. Altinel. A design flow for predictable composable systems. Master's thesis, KTH, School of Information and Communication Technology (ICT), 2013. [ bib ]
design flow, synthesis
[9] J. Zhu, I. Sander, and A. Jantsch. Performance analysis of reconfigurations in adaptive real-time streaming applications. ACM Transactions on Embedded Computing Systems, 11S(1):12:1--12:20, June 2012. [ bib | DOI | http ]
design flow, analysis and dse
[10] G. Hjort Blindell. Synthesizing software from a forsyde model targeting GPGPUs, 2012. [ bib ]
design flow, synthesis
[11] G. S. Beserra, S. H. Attarzadeh Niaki, and I. Sander. Integrating virtual platforms into a heterogeneous MoC-based modeling framework. In Forum on Specification and Design Languages (FDL 2012), pages 143--150, Vienna, Austria, 2012. [ bib ]
design flow, simulation
[12] S. H. Attarzadeh Niaki and I. Sander. Semi-formal refinement of heterogeneous embedded systems by foreign model integration. In Proceedings of Forum for Design Languages (FDL '11), Oldenburg, Germany, September 2011. [ bib ]
design flow, refinement
[13] S. H. Attarzadeh Niaki and I. Sander. Co-simulation of embedded systems in a heterogeneous MoC-based modeling framework. In 6th IEEE International Symposium on Industrial Embedded Systems (SIES 2011), pages 238--247. IEEE, June 2011. [ bib | DOI ]
design flow, simulation
[14] J. Zhu, I. Sander, and A. Jantsch. Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs. In Design Automation and Test in Europe (DATE '10), Dresden, Germany, March 2010. [ bib | .pdf ]
design flow, analysis and dse
[15] J. Zhu, I. Sander, and A. Jantsch. Constrained global scheduling of streaming applications on MPSoCs. In Asia South Pacific Design Automation Conference (ASP-DAC '10), 2010. [ bib | DOI ]
design flow, analysis and dse
[16] I. Sander, J. Zhu, A. Jantsch, A. Herrholz, P. A. Hartmann, and W. Nebel. High-level estimation and trade-off analysis for adaptive real-time systems. In Proceedings of the 16th Reconfigurable Architectures Workshop (RAW 2009), pages 1--4, Rome, Italy, May 2009. [ bib | DOI ]
design flow, adaptivity, analysis and dse
[17] J. Zhu, I. Sander, and A. Jantsch. Buffer minimization of real-time streaming applications on hybrid CPU/FPGA. In Design Automation and Test in Europe (DATE'09), pages 1506--1511, Nice, France, 2009. [ bib | .pdf ]
design flow, analysis and dse
[18] J. Zhu, I. Sander, and A. Jantsch. Energy efficient streaming applications with guaranteed throughput on MPSoCs. In Proceedings of the International Conference on Embedded Software (EMSOFT'08), Atlanta, USA, October 2008. [ bib | DOI ]
design flow, analysis and dse
[19] J. Zhu, I. Sander, and A. Jantsch. Performance analysis of reconfiguration in adaptive real-time streaming applications. In Proceedings of the 6th Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia'08), Atlanta, USA, October 2008. [ bib | .pdf ]
design flow, analysis and dse
[20] T. Raudvere, I. Sander, and A. Jantsch. Application and verification of local non-semantic-preserving transformations in system design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(6):1091--1103, June 2008. [ bib | DOI ]
design flow, verification
[21] T. Raudvere, I. Sander, and A. Jantsch. Synchronization after design refinements with sensitive delay elements. In International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), Salzburg, Austria, October 2007. [ bib | DOI ]
design flow, refinement
[22] Z. Lu, J. Sicking, I. Sander, and A. Jantsch. Using synchronizers for refining synchronous communication onto hardware/software architectures. In Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP'07), Porto Alegre, Brazil, May 2007. [ bib | DOI ]
design flow, refinement
[23] T. Raudvere, I. Sander, and A. Jantsch. A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops. In Proceedings of the 17th Great Lakes Symposium on VLSI (GLSVLSI '07), pages 353--358, 2007. [ bib | DOI ]
design flow, refinement
[24] A. Acosta. Hardware synthesis in ForSyDe. Master's thesis, School for Information and Communication Technology, Royal Institute of Technology (KTH), Stockholm, Sweden, 2007. KTH/ICT/ECS-2007-81. [ bib | .pdf ]
design flow, synthesis
[25] Z. Lu, I. Sander, and A. Jantsch. Towards performance-oriented pattern-based refinement of synchronous models onto NoC communication. In Proceedings of the 9th Euromicro Conference on Digital System Design (DSD'06), Dubrovnik, Croatia, August 2006. [ bib | .pdf ]
design flow, refinement
[26] Z. Lu, I. Sander, and A. Jantsch. Refining synchronous communication onto network-on-chip best-effort services. In Advances in Design and Specification Languages for SoCs - Selected Contributions from FDL 2005. Springer Verlag, April 2006. [ bib | DOI ]
design flow, refinement
[27] T. Raudvere, A. K. Singh, I. Sander, and A. Jantsch. System level verification of digital signal processing applications based on the polynomial abstraction technique. In International Conference on Computer Aided Design (ICCAD 2005), November 2005. [ bib | DOI ]
design flow, verification
[28] Z. Lu, I. Sander, and A. Jantsch. Refinement of a perfectly synchronous communication model onto Nostrum NoC best-effort communication. In Proceedings of the Forum on Specification and Design Languages (FDL'05), September 2005. [ bib | .pdf ]
design flow, refinement
[29] T. Raudvere, A. K. Singh, I. Sander, and A. Jantsch. Polynomial abstraction for verification of sequentially implemented combinational circuits. In Design, Automation and Test in Europe Conference (DATE 2004), Paris, France, February 2004. [ bib | DOI ]
design flow, verification
[30] I. Sander and A. Jantsch. System modeling and transformational design refinement in ForSyDe. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(1):17--32, January 2004. [ bib | DOI ]
design flow, modeling, refinement
[31] T. Raudvere, I. Sander, A. K. Singh, and A. Jantsch. Verification of design decisions in ForSyDe. In Proceedings of the 1st International Conference on Hardware - Software Codesign and System Synthesis (CODES+ISSS), Newport Beach, California, USA, October 2003. [ bib | DOI ]
design flow, verification
[32] I. Sander, A. Jantsch, and Z. Lu. Development and application of design transformations in ForSyDe. IEE Proceedings - Computers & Digital Techniques, 5:313--320, September 2003. Special Issue - Best of DATE '03. [ bib | DOI ]
design flow, refinement
[33] I. Sander. System Modeling and Design Refinement in ForSyDe. PhD thesis, Royal Institute of Technology, Stockholm, Sweden, April 2003. [ bib | .pdf ]
design flow, modeling, refinement, synthesis
[34] I. Sander, A. Jantsch, and Z. Lu. Development and application of design transformations in ForSyDe. In Design, Automation and Test in Europe Conference (DATE 2003), pages 364--369, Munich, Germany, March 2003. [ bib | DOI ]
design flow, refinement
[35] Z. Lu, I. Sander, and A. Jantsch. A case study of hardware and software synthesis in ForSyDe. In Proceedings of the 15th International Symposium on System Synthesis, pages 86--91, Kyoto, Japan, October 2002. [ bib | DOI ]
design flow, synthesis
[36] I. Sander and A. Jantsch. Transformation based communication and clock domain refinement for system design. In 39th Design Automation Conference (DAC 2002), pages 281--286, New Orleans, USA, June 2002. [ bib | DOI ]
design flow, refinement
[37] W. Wu, I. Sander, and A. Jantsch. Transformational system design based on a formal computational model and skeletons. In Forum on Design Languages 2000, pages 321--328, Tübingen, Germany, September 2000. [ bib | .pdf ]
design flow, refinement
[38] I. Sander and A. Jantsch. System synthesis utilizing a layered functional model. In Proceedings Seventh International Workshop on Hardware/Software Codesign, pages 136--140, Rome, Italy, May 1999. ACM Press. [ bib | DOI ]
design flow, synthesis
[39] I. Sander and A. Jantsch. System synthesis based on a formal computational model and skeletons. In Proceedings IEEE Workshop on VLSI'99, pages 32--39, Orlando, Florida, USA, April 1999. IEEE Computer Society. [ bib | DOI ]
design flow, synthesis
[40] I. Sander and A. Jantsch. Formal system design based on the synchrony hypothesis, functional models, and skeletons. In Proceedings of the 12th international conference on VLSI Design, pages 318--323, Goa, India, January 1999. IEEE Computer Society. [ bib | DOI ]
design flow, modeling