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[1]
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T. Raudvere, I. Sander, and A. Jantsch.
Application and verification of local non-semantic-preserving
transformations in system design.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 27(6):1091--1103, June 2008.
[ bib |
DOI ]
design flow, verification
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[2]
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T. Raudvere, A. K. Singh, I. Sander, and A. Jantsch.
System level verification of digital signal processing applications
based on the polynomial abstraction technique.
In International Conference on Computer Aided Design (ICCAD
2005), November 2005.
[ bib |
DOI ]
design flow, verification
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[3]
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T. Raudvere, A. K. Singh, I. Sander, and A. Jantsch.
Polynomial abstraction for verification of sequentially implemented
combinational circuits.
In Design, Automation and Test in Europe Conference (DATE
2004), Paris, France, February 2004.
[ bib |
DOI ]
design flow, verification
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[4]
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T. Raudvere, I. Sander, A. K. Singh, and A. Jantsch.
Verification of design decisions in ForSyDe.
In Proceedings of the 1st International Conference on Hardware -
Software Codesign and System Synthesis (CODES+ISSS), Newport Beach,
California, USA, October 2003.
[ bib |
DOI ]
design flow, verification
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