New IDeSyDe and ForSyDe IO releases

Wed, 29 May 2024 11:00:00 +0000

We are happy to annouce the newer releases of IDeSyDe and ForSyDe IO. These newest releases enables you to solve DSE scenarios where the applications are modelled as SDF graphs and the platform contains FPGA elements which can host actors synthetized as ASICs. Naturally, this happens at the system-level, which means that the IDeSyDe makes mapping judgments based on number estimates and not on actual synthesis results. On the other hand, this has the advantage that you can use the DSE approach of this latest release with estimates of performance, in earlier stages of your design process.

IDeSyDe: latest releases and publications

Wed, 14 Jun 2023 11:00:00 +0000

IDeSyDe 0.5.9 has been released. It has many changes since the last update in October 2022, including a multi-modular architecture that enables dynamic use of identification and exploration modules. Check out the releases and the documentation for more information.

This latest release is also featured in DASC 2023!

IDeSyDe and ForSyDe IO: latest releases and publications

Sun, 02 Oct 2022 11:00:00 +0000

Since 2019 we have been developing two new entries in the tools ecosystem, based on lessons learned from previous years and tools. These two entries are IDeSyDe and ForSyDe IO.

IDeSyDe is the current design space exploration tool in ForSyDe design flow. It is based on the concept of design space identification in order to systematically combine and extend different design space exploration scenarios without sacrificing exploration performance. The accompanying publication, accepted, presented and published in DATE 2021, can be found here and it is also listed in publications.

ForSyDe IO is the candidate for a common exchange model in the tools ecosystem; as currently not all tools can connect its results to the inputs of another. The accompanying publication was accepted and presented in FDL 2022, in Linz, Austria. Once it is also published in the proceedings of the conference, the publication will be added to the ForSyDe IO project website.

You can follow the active development and specific documemtation for each of these two projects in their websites.

ForSyDe lives!

Mon, 01 Nov 2021 11:00:00 +0000

It has been a long time since we last posted here. Luckily, it was for all the good reasons! The major one is research. Sometimes a deep focus is required. And sadly, that might mean long hiatus between front-page updates.

Here are some noteworthy news since Sept. 2019, the date of our last update:

We published a paper about “design space identification”. It is the method that underpines our new design space exploration tool: IDeSyDe. Here’s a quick citation, for your knowledge:

Jordão, R.; Sander, I. & Becker, M. Formulation of Design Space Exploration Problems by Composable Design Space Identification 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, 1204-1207
We started two new “tool” projects (see one above):
- IDeSyDe, the new DSE tool from our group after DeSyDe.
- ForSyDe-IO, our “intermediate” model representation supporting libs.
We are part of two projects that gives our continous knowledge transfer with industry:
- ITEA3 PANORAMA
- VINNOVA EARLY BIRD

To close this brief “I’m alive!” post, it is nice to remind the reader of another place where a lot of our activity is destined to: Our organization github!

That’s all for now, see you next time!

FDL2019 Best Paper Award

Thu, 05 Sep 2019 11:00:00 +0000

We are happy to announce that our paper got the “Best Paper Award” at the Forum on specification & Design Languages (FDL2019) in Southampton, United Kingdomm on September 2-4, 2019:

George Ungureanu, Timmy Sundström, Anders Åhlander, Ingo Sander and Ingemar Söderquist. 2019. Formal Design, Co-Simulation and Validation of a Radar Signal Processing System. Proceedings of the Forum on specification & Design Languages [DOI|url|bib|slides]

This paper has been written in collaboration with our industrial partners at Saab AB, and summarizes the work and results presented in the “Design of Sensor Signal Processing with ForSyDe: Modeling, Validation and Synthesis” technical report. The friendly atmosphere at FDL spawned many interesting discussions and we are grateful that we got the chance to meet, discuss and present next to top researchers in our community.

ACM TODAES Paper

Wed, 21 Aug 2019 11:00:00 +0000

We are happy to announce that the following paper has been published in ACM Transactions on Design Automation of Electronic Systems (TODAES):

Ricardo Bonna, Denis S. Loubach, George Ungureanu, and Ingo Sander. 2019. Modeling and Simulation of Dynamic Applications Using Scenario-Aware Dataflow. ACM Trans. Des. Autom. Electron. Syst. 24, 5, Article 58 (August 2019), 29 pages. [DOI|url|bib]

DeSyDe 0.3.0 Release

Tue, 19 Feb 2019 00:00:00 +0000

A new version of DeSyDe has been released recently, compatible with and supporting our latest DSD’18 publication: K. Rosvall et al., ‘Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors’.

This version is accompanied by:

a reproducible set of experiments, as presented in the DSD’18 paper;
a set of scripts for generating experiments based on the template above, but for different TDN-NoC platform dimensions;
a hands-on user tutorial which guides newcomers through using the tool and interpreting the output.

This release will most likely be stale for a while or will only be followed by minor fixes. At present we are discussing a complete re-design of the tool itself (for scalability and maintainability purpose), which will certainly take significant development effort, so no new major updates are planned for the near future.

New web pages and tool releases

Sun, 30 Dec 2018 00:00:00 +0000

The ForSyDe Web Site is Growing

We conclude a very busy and intense year, 2018, with announcing some new web content which has finally been compiled together or migrated from old repositories. We are still in the (long) process of exposing and documenting our tools and methods better, and the progress can only done in “baby steps” due to the ruthless workloads here in academia. Nevertheless, we proudly present that:

The ForSyDe welcome page has now relevant content.
The ForSyDe-Shallow project has finally received an own page.
The same goes for ForSyDe-Deep which has also a web page gathering important resources.

New Public Releases

As of recent tool maintenance, we have published the following Haskell packages on HackageDB:

ForSyDe-Shallow v.3.3.3 adding the CSDF and SADF MoCs, contribution by Ricardo Bonna;
ForSyDe-Deep v.0.2 is finally on HackageDB;
the old ForSyDe package has been formally tagged as deprecated in favor of the aforementioned ones.

ForSyDe-Shallow 3.3.3.0 Update

Wed, 10 Oct 2018 00:00:00 +0000

ForSyDe-Shallow Update

ForSyDe-Shallow has been updated to version 3.3.3, which adds the following features:

a modeling library for the scenario-aware dataflow (SADF) MoC
a modeling library for the cyclo-static data flow (CSDF) MoC

Currently, this version of ForSyDe-Shallow is only available as a nightly build. We are currently working on the 3.4.0 release, which will be available through HackageDB. In the meantime we will keep you up to date.

In the following days an SADF example will also be added to the forsyde-shallow-examples repository.

DSD/SEAA 2018 Paper

Mon, 03 Sep 2018 11:00:00 +0000

We have presented the following paper at the Euromicro DSD/SEAA 2018 conference which took place in Prague, Czech Republic, between the 29th and the 30th of August:

Kathrin Rosvall, Tage Mohammadat, George Ungureanu, Johnny Öberg and Ingo Sander. 2018. Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors. [url|bib]

The manuscript have been published in the 2018 21st Euromicro Conference on Digital System Design (DSD), and can be viewed by following the URL above.