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[1]
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G. Ungureanu, T. Sundström, A. Ahlander, I. Sander, and
I. Söderquist.
Formal design, co-simulation and validation of a radar signal
processing system.
In 2019 Forum for Specification and Design Languages (FDL),
pages 1--8, Sep. 2019.
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DOI |
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modeling, design flow, synthesis
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[2]
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G. Ungureanu, T. Sundström, A. Ahlander, I. Sander, and
I. Söderquist.
Design of sensor signal processing with ForSyDe: Modeling,
validation and synthesis.
Technical report, KTH Royal Institute of Tehnology, 2019.
[ bib |
DOI |
http ]
modeling, design flow, synthesis
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[3]
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G. H. Blindell, C. Menne, and I. Sander.
Languages, Design Methods, and Tools for Electronic System
Design, chapter Synthesizing Code for GPGPUs from Abstract Formal Models,
pages 115--134.
Springer, 2016.
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synthesis
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[4]
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S. H. Attarzadeh Niaki, M. Mikulcak, and I. Sander.
Languages, Design Methods, and Tools for Electronic System
Design, chapter Automatic Generation of Virtual Prototypes from Platform
Templates, pages 147--166.
Springer, 2015.
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synthesis
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[5]
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G. H. Blindell, C. Menne, and I. Sander.
Synthesizing code for GPGPUs from abstract formal models.
In Forum on Specification and Design Languages (FDL 2014),
Munich, Germany, Oct. 2014.
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synthesis
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[6]
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G. Ungureanu.
Automatic software synthesis from high-level forsyde models targeting
massively parallel processors.
Master's thesis, KTH, School of Information and Communication
Technology (ICT), 2013.
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design flow, synthesis
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[7]
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M. Mikulcak.
Development of a predictable hardware architecture template and
integration into an automated system design flow.
Master's thesis, KTH, School of Information and Communication
Technology (ICT), 2013.
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design flow, synthesis
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[8]
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E. Altinel.
A design flow for predictable composable systems.
Master's thesis, KTH, School of Information and Communication
Technology (ICT), 2013.
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design flow, synthesis
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[9]
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G. Hjort Blindell.
Synthesizing software from a forsyde model targeting GPGPUs, 2012.
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design flow, synthesis
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[10]
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A. Acosta.
Hardware synthesis in ForSyDe.
Master's thesis, School for Information and Communication Technology,
Royal Institute of Technology (KTH), Stockholm, Sweden, 2007.
KTH/ICT/ECS-2007-81.
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.pdf ]
design flow, synthesis
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[11]
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I. Sander.
System Modeling and Design Refinement in ForSyDe.
PhD thesis, Royal Institute of Technology, Stockholm, Sweden, April
2003.
[ bib |
.pdf ]
design flow, modeling, refinement, synthesis
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[12]
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Z. Lu, I. Sander, and A. Jantsch.
A case study of hardware and software synthesis in ForSyDe.
In Proceedings of the 15th International Symposium on System
Synthesis, pages 86--91, Kyoto, Japan, October 2002.
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DOI ]
design flow, synthesis
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[13]
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I. Sander and A. Jantsch.
System synthesis utilizing a layered functional model.
In Proceedings Seventh International Workshop on
Hardware/Software Codesign, pages 136--140, Rome, Italy, May 1999. ACM
Press.
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DOI ]
design flow, synthesis
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[14]
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I. Sander and A. Jantsch.
System synthesis based on a formal computational model and skeletons.
In Proceedings IEEE Workshop on VLSI'99, pages 32--39,
Orlando, Florida, USA, April 1999. IEEE Computer Society.
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DOI ]
design flow, synthesis
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