The ForSyDe-Deep is the deep-embedded counterpart of ForSyDe-Shallow, and is able to both simulate and synthesize a subset of the ForSyDe language. It currently supports two backend formats for synthesis:
- VHDL code describing digital hardware;
- GraphML structure representing the ForSyDe process network.
Among the features of ForSyDe-Deep, we can highlight the following:
- it recognizes synchronous (SY) process constructors and is able to generate corresponding backend templates.
- it supports skeletons on vectors which are higher-order functions which create regular parallel structures of components.
- it parses a subset of the Haskell language, captured by functions passed as arguments to process constructors, using Template Haskell, and is able to synthesize equivalent backend code.
- it provides a rich set of utilities for compiling or simulating the generated VHDL code using ModelSim or the Intel Quartus tool suite.
Due to numerous dependencies on Template Haskell, ForSyDe-Deep is only compatible with versions 7.10.3 or 8.0.1 of the GHC compiler. Because of this, we recommend installing the libraries and tools as a Stack project. The quickest way to test ForSyDe-Deep is to clone or download the project, as it has all the dependencies already set, and run one of the available examples in a sandboxed environment. To do this, after you acquire the source code, type in
cd path/to/forsyde-deep stack update stack install
and wait until the installation is complete. Load one of the example designs in an interpreter session. E.g.:
stack ghci examples/FoldlVector.hs
which contains the design of a combinational system which sums the elements of a vector with length 4, defined along the lines of:
Inside the interpreter session load the
ForSyDe.Deep and the
> :m +ForSyDe.Deep Data.Param.FSVec
Let’s create three test
FSVectors to simulate against the
> let x1 = 1 +> 2 +> 3 +> 4 +> empty -- <1,2,3,4> > let x2 = 2 +> 3 +> 4 +> 5 +> empty -- <2,3,4,5> > let x3 = 10 +> 11 +> 12 +> 13 +> empty -- <10,11,12,13> > simulate foldingAdderSys $ [x1, x2, x3] [10,14,46]
You can also dump the complete functional VHDL files or the GraphML structure directly with:
> writeVHDL foldingAdderSys > writeGraphML foldingAdderSys
Check out the dumped files. You can open them in any appropriate editor or tool suite. To make use of the utilities for passing the design to tools like Quartus or ModelSim, or for tips on visualizing the system structure please follow the tutorials pointed below.
Documentation and Resources
Here you can find links to further documentation resources: