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[1]
|
R. Bonna, D. S. Loubach, G. Ungureanu, and I. Sander.
Modeling and simulation of dynamic applications using scenario-aware
dataflow.
ACM Trans. Des. Autom. Electron. Syst., 24(5):58:1--58:29, Aug.
2019.
[ bib |
DOI |
http ]
modeling
|
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[2]
|
G. Ungureanu, T. Sundström, A. Ahlander, I. Sander, and
I. Söderquist.
Formal design, co-simulation and validation of a radar signal
processing system.
In 2019 Forum for Specification and Design Languages (FDL),
pages 1--8, Sep. 2019.
[ bib |
DOI |
http ]
modeling, design flow, synthesis
|
|
[3]
|
G. Ungureanu, T. Sundström, A. Ahlander, I. Sander, and
I. Söderquist.
Design of sensor signal processing with ForSyDe: Modeling,
validation and synthesis.
Technical report, KTH Royal Institute of Tehnology, 2019.
[ bib |
DOI |
http ]
modeling, design flow, synthesis
|
|
[1]
|
J. E. G. de Medeiros, G. Ungureanu, and I. Sander.
An algebra for modeling continuous time systems.
In Design Automation and Test in Europe (DATE 2018),
Dresden, Germany, March 2018.
Accepted for publication as interactive presentation paper.
[ bib |
DOI ]
modeling
|
|
[2]
|
G. Ungureanu, J. E. G. de Medeiros, and I. Sander.
Bridging discrete and continuous time models with Atoms.
In 2018 Design, Automation Test in Europe Conference
Exhibition (DATE), Dresden, Germany, March 2018.
Accepted for publication as interactive presentation paper.
[ bib |
DOI ]
modeling
|
|
[3]
|
K. Rosvall, T. Mohammadat, G. Ungureanu, J. Öberg, and I. Sander.
Exploring power and throughput for dataflow applications on
predictable noc multiprocessors.
In 2018 21st Euromicro Conference on Digital System Design
(DSD), pages 719--726, Aug 2018.
[ bib |
DOI ]
analysis and dse
|
|
[1]
|
G. Ungureanu and I. Sander.
A layered formal framework for modeling of cyber-physical systems.
In Design Automation and Test in Europe (DATE 2017),
Lausanne, Switzerland, Mar. 2017.
[ bib ]
modeling
|
|
[2]
|
S.-H. Attarzadeh-Niaki and I. Sander.
Automatic construction of models for analytic system-level design
space exploration problems.
In Design Automation and Test in Europe (DATE 2017),
Lausanne, Switzerland, Mar. 2017.
[ bib ]
analysis and dse
|
|
[3]
|
K. Rosvall, N. Khalilzad, G. Ungureanu, and I. Sander.
Throughput propagation in constraint-based design space exploration
for mixed-criticality systems.
In Proceedings of the 2017 Workshop on Rapid Simulation and
Performance Evaluation: Methods and Tools, RAPIDO '17, Stockholm, Sweden,
January 2017.
[ bib ]
analysis and dse
|
|
[4]
|
K. Rosvall and I. Sander.
Flexible and trade-off-aware constraint-based design space
exploration for streaming applications on heterogeneous platforms.
ACM Transactions on Design Automation of Electronic Systems
(TODAES), 2017.
Accepted for publication.
[ bib ]
analysis and dse
|
|
[5]
|
I. Sander, A. Jantsch, and S.-H. Attarzadeh-Niaki.
ForSyDe: System design using a functional language and models of
computation.
In S. Ha and J. Teich, editors, Handbook of Hardware/Software
Codesign, pages 99--140. Springer Netherlands, 2017.
[ bib ]
design flow, modeling
|
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[6]
|
S.-H. Attarzadeh-Niaki, E. Altinel, M. Koedam, A. Molnos, I. Sander, and
K. Goossens.
A Composable and Predictable MPSoC Design Flow for Multiple
Real-Time Applications, pages 157--174.
Springer International Publishing, Cham, 2017.
[ bib |
DOI |
http ]
design flow
|
|
[1]
|
N. Khalilzad, K. Rosvall, and I. Sander.
A modular design space exploration framework for multiprocessor
real-time systems.
In Forum on Specification and Design Languages (FDL 2016),
Bremen, Germany, Sept. 2016.
[ bib ]
analysis and dse
|
|
[2]
|
S. Attarzadeh-Niaki and I. Sander.
An extensible modeling methodology for embedded and cyber-physical
system design.
SIMULATION: Transactions of The Society for Modeling and
Simulation International, 92(8):771--794, 2016.
[ bib |
DOI ]
modeling
|
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[3]
|
G. H. Blindell, C. Menne, and I. Sander.
Languages, Design Methods, and Tools for Electronic System
Design, chapter Synthesizing Code for GPGPUs from Abstract Formal Models,
pages 115--134.
Springer, 2016.
[ bib ]
synthesis
|
|
[1]
|
S. Attarzadeh-Niaki and I. Sander.
Integrating functional mock-up units into a formal heterogeneous
system modeling framework.
In International Symposium on Computer Architecture and Digital
Systems (CADS), Oct. 2015.
[ bib |
DOI ]
modeling
|
|
[2]
|
P. Diallo, S.-H. Attarzadeh-Niaki, F. Robino, I. Sander, J. Champeau, and
J. Öberg.
A formal, model-driven design flow for system simulation and
multi-core implementation.
In Symposium on Industrial Embedded Systems (SIES), Siegen,
Germany, June 2015.
[ bib |
DOI ]
design flow
|
|
[3]
|
F. Herrera, K. Rosvall, I. Sander, E. Paone, and G. Palermo.
An efficient joint analytical and simulation-based design space
exploration flow for predictable multi-core systems.
In Workshop on Rapid Simulation and Performance Evaluation:
Methods and Tools (RAPIDO), Amsterdam, The Netherlands, Jan. 2015.
[ bib |
DOI ]
analysis and dse
|
|
[4]
|
F. Herrera and I. Sander.
Languages, Design Methods, and Tools for Electronic System
Design, chapter Combining Analytical and Simulation-Based Design Space
Exploration for Efficient Time-Critical and Mixed-Criticality Systems, pages
167--188.
Springer, 2015.
[ bib ]
analysis and dse
|
|
[5]
|
S. H. Attarzadeh Niaki, M. Mikulcak, and I. Sander.
Languages, Design Methods, and Tools for Electronic System
Design, chapter Automatic Generation of Virtual Prototypes from Platform
Templates, pages 147--166.
Springer, 2015.
[ bib ]
synthesis
|
|
[1]
|
F. Herrera and I. Sander.
An extensible infrastructure for modeling and time analysis of
predictable embedded systems.
In Forum on Specification and Design Languages (FDL 2014),
Munich, Germany, Oct. 2014.
[ bib |
DOI ]
modeling, analysis and dse
|
|
[2]
|
G. H. Blindell, C. Menne, and I. Sander.
Synthesizing code for GPGPUs from abstract formal models.
In Forum on Specification and Design Languages (FDL 2014),
Munich, Germany, Oct. 2014.
[ bib |
DOI ]
synthesis
|
|
[3]
|
K. Rosvall and I. Sander.
A constraint-based design space exploration framework for real-time
applications on MPSoCs.
In Design Automation and Test in Europe (DATE '14),
Dresden, Germany, Mar. 2014.
[ bib |
DOI ]
analysis and dse
|
|
[1]
|
S. H. Attarzadeh Niaki, M. Mikulcak, and I. Sander.
Rapid virtual prototyping of real-time systems using predictable
platform characterizations.
In Forum on Specification and Design Languages (FDL 2013),
Paris, France, Sept. 2013.
[ bib ]
design flow, simulation
|
|
[2]
|
S. H. Attarzadeh Niaki and I. Sander.
An automated parallel simulation flow for heterogeneous embedded
systems.
In Proceedings of Design Automation and Test in Europe
(DATE '13), pages 27--30, Grenoble, France, March 2013.
[ bib ]
design flow, simulation
|
|
[3]
|
G. Ungureanu.
Automatic software synthesis from high-level forsyde models targeting
massively parallel processors.
Master's thesis, KTH, School of Information and Communication
Technology (ICT), 2013.
[ bib ]
design flow, synthesis
|
|
[4]
|
M. Mikulcak.
Development of a predictable hardware architecture template and
integration into an automated system design flow.
Master's thesis, KTH, School of Information and Communication
Technology (ICT), 2013.
[ bib ]
design flow, synthesis
|
|
[5]
|
E. Altinel.
A design flow for predictable composable systems.
Master's thesis, KTH, School of Information and Communication
Technology (ICT), 2013.
[ bib ]
design flow, synthesis
|
|
[1]
|
J. Zhu, I. Sander, and A. Jantsch.
Performance analysis of reconfigurations in adaptive real-time
streaming applications.
ACM Transactions on Embedded Computing Systems,
11S(1):12:1--12:20, June 2012.
[ bib |
DOI |
http ]
design flow, analysis and dse
|
|
[2]
|
M. K. Jakobsen, J. Madsen, S. H. Attarzadeh Niaki, I. Sander, and J. Hansen.
System level modelling with open source tools.
In Embedded World, Nuremberg, Germany, February 2012.
[ bib |
.pdf ]
modeling
|
|
[3]
|
G. Hjort Blindell.
Synthesizing software from a forsyde model targeting GPGPUs, 2012.
[ bib ]
design flow, synthesis
|
|
[4]
|
S. Attarzadeh Niaki, M. Jakobsen, T. Sulonen, and I. Sander.
Formal heterogeneous system modeling with SystemC.
In Forum on Specification and Design Languages (FDL 2012),
pages 160--167, Vienna, Austria, 2012.
[ bib ]
modeling
|
|
[5]
|
G. S. Beserra, S. H. Attarzadeh Niaki, and I. Sander.
Integrating virtual platforms into a heterogeneous MoC-based
modeling framework.
In Forum on Specification and Design Languages (FDL 2012),
pages 143--150, Vienna, Austria, 2012.
[ bib ]
design flow, simulation
|
|
[6]
|
S. H. Attarzadeh Niaki, G. S. Beserra, N. Andersen, M. Verdon, and I. Sander.
Heterogeneous system-level modeling for small and medium enterprises.
In 25th Symposium on Integrated Circuits and Systems Design
(SBCCI 2012), pages 1--6, Brasilia, Brazil, 2012.
[ bib |
DOI ]
modeling
|
|
[1]
|
S. H. Attarzadeh Niaki and I. Sander.
Semi-formal refinement of heterogeneous embedded systems by foreign
model integration.
In Proceedings of Forum for Design Languages (FDL '11),
Oldenburg, Germany, September 2011.
[ bib ]
design flow, refinement
|
|
[2]
|
S. H. Attarzadeh Niaki and I. Sander.
Co-simulation of embedded systems in a heterogeneous MoC-based
modeling framework.
In 6th IEEE International Symposium on Industrial Embedded
Systems (SIES 2011), pages 238--247. IEEE, June 2011.
[ bib |
DOI ]
design flow, simulation
|
|
[1]
|
J. Zhu, I. Sander, and A. Jantsch.
HetMoC: heterogeneous modelling in SystemC.
In Proceedings of Forum for Design Languages (FDL '10),
Southampton, UK, September 2010.
[ bib |
.pdf ]
modeling
|
|
[2]
|
J. Zhu, I. Sander, and A. Jantsch.
Pareto efficient design for reconfigurable streaming applications
on CPU/FPGAs.
In Design Automation and Test in Europe (DATE '10),
Dresden, Germany, March 2010.
[ bib |
.pdf ]
design flow, analysis and dse
|
|
[3]
|
J. Zhu, I. Sander, and A. Jantsch.
Constrained global scheduling of streaming applications on MPSoCs.
In Asia South Pacific Design Automation Conference
(ASP-DAC '10), 2010.
[ bib |
DOI ]
design flow, analysis and dse
|
|
[1]
|
I. Sander, J. Zhu, A. Jantsch, A. Herrholz, P. A. Hartmann, and W. Nebel.
High-level estimation and trade-off analysis for adaptive real-time
systems.
In Proceedings of the 16th Reconfigurable Architectures Workshop
(RAW 2009), pages 1--4, Rome, Italy, May 2009.
[ bib |
DOI ]
design flow, adaptivity, analysis and dse
|
|
[2]
|
J. Zhu, I. Sander, and A. Jantsch.
Buffer minimization of real-time streaming applications on hybrid
CPU/FPGA.
In Design Automation and Test in Europe (DATE'09), pages
1506--1511, Nice, France, 2009.
[ bib |
.pdf ]
design flow, analysis and dse
|
|
[1]
|
J. Zhu, I. Sander, and A. Jantsch.
Energy efficient streaming applications with guaranteed throughput on
MPSoCs.
In Proceedings of the International Conference on Embedded
Software (EMSOFT'08), Atlanta, USA, October 2008.
[ bib |
DOI ]
design flow, analysis and dse
|
|
[2]
|
J. Zhu, I. Sander, and A. Jantsch.
Performance analysis of reconfiguration in adaptive real-time
streaming applications.
In Proceedings of the 6th Workshop on Embedded Systems for
Real-Time Multimedia (ESTIMedia'08), Atlanta, USA, October 2008.
[ bib |
.pdf ]
design flow, analysis and dse
|
|
[3]
|
T. Raudvere, I. Sander, and A. Jantsch.
Application and verification of local non-semantic-preserving
transformations in system design.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 27(6):1091--1103, June 2008.
[ bib |
DOI ]
design flow, verification
|
|
[4]
|
I. Sander and A. Jantsch.
Modelling adaptive systems in ForSyDe.
Electronic Notes in Theoretical Computer Science (ENTCS),
200(2):39--54, 2008.
First Workshop on Verification of Adaptive Systems (VerAS 2007).
[ bib |
DOI |
.pdf ]
modeling, adaptivity
|
|
[1]
|
T. Raudvere, I. Sander, and A. Jantsch.
Synchronization after design refinements with sensitive delay
elements.
In International Conference on Hardware-Software Codesign and
System Synthesis (CODES+ISSS), Salzburg, Austria, October 2007.
[ bib |
DOI ]
design flow, refinement
|
|
[2]
|
Z. Lu, J. Sicking, I. Sander, and A. Jantsch.
Using synchronizers for refining synchronous communication onto
hardware/software architectures.
In Proceedings of the 18th IEEE/IFIP International Workshop on
Rapid System Prototyping (RSP'07), Porto Alegre, Brazil, May 2007.
[ bib |
DOI ]
design flow, refinement
|
|
[3]
|
T. Raudvere, I. Sander, and A. Jantsch.
A synchronization algorithm for local temporal refinements in
perfectly synchronous models with nested feedback loops.
In Proceedings of the 17th Great Lakes Symposium on VLSI
(GLSVLSI '07), pages 353--358, 2007.
[ bib |
DOI ]
design flow, refinement
|
|
[4]
|
A. Acosta.
Hardware synthesis in ForSyDe.
Master's thesis, School for Information and Communication Technology,
Royal Institute of Technology (KTH), Stockholm, Sweden, 2007.
KTH/ICT/ECS-2007-81.
[ bib |
.pdf ]
design flow, synthesis
|
|
[1]
|
Z. Lu, I. Sander, and A. Jantsch.
Towards performance-oriented pattern-based refinement of synchronous
models onto NoC communication.
In Proceedings of the 9th Euromicro Conference on Digital System
Design (DSD'06), Dubrovnik, Croatia, August 2006.
[ bib |
.pdf ]
design flow, refinement
|
|
[2]
|
Z. Lu, I. Sander, and A. Jantsch.
Refining synchronous communication onto network-on-chip best-effort
services.
In Advances in Design and Specification Languages for SoCs -
Selected Contributions from FDL 2005. Springer Verlag, April 2006.
[ bib |
DOI ]
design flow, refinement
|
|
[1]
|
T. Raudvere, A. K. Singh, I. Sander, and A. Jantsch.
System level verification of digital signal processing applications
based on the polynomial abstraction technique.
In International Conference on Computer Aided Design (ICCAD
2005), November 2005.
[ bib |
DOI ]
design flow, verification
|
|
[2]
|
Z. Lu, I. Sander, and A. Jantsch.
Refinement of a perfectly synchronous communication model onto
Nostrum NoC best-effort communication.
In Proceedings of the Forum on Specification and Design
Languages (FDL'05), September 2005.
[ bib |
.pdf ]
design flow, refinement
|
|
[3]
|
A. Jantsch and I. Sander.
Models of computation and languages for embedded system design.
IEE Proceedings on Computers and Digital Techniques,
152(2):114--129, Mar. 2005.
[ bib |
DOI ]
modeling
|
|
[4]
|
A. Jantsch.
Models of embedded computation.
In R. Zurawski, editor, Embedded Systems Handbook. CRC Press,
2005.
Invited contribution.
[ bib |
.pdf ]
modeling
|
|
[5]
|
A. Jantsch and I. Sander.
Models of computation in the design process.
In B. M. Al-Hashimi, editor, SoC: Next Generation Electronics.
IEE, 2005.
Invited contribution.
[ bib |
.pdf ]
modeling
|
|
[1]
|
T. Raudvere, A. K. Singh, I. Sander, and A. Jantsch.
Polynomial abstraction for verification of sequentially implemented
combinational circuits.
In Design, Automation and Test in Europe Conference (DATE
2004), Paris, France, February 2004.
[ bib |
DOI ]
design flow, verification
|
|
[2]
|
I. Sander and A. Jantsch.
System modeling and transformational design refinement in ForSyDe.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 23(1):17--32, January 2004.
[ bib |
DOI ]
design flow, modeling, refinement
|
|
[1]
|
T. Raudvere, I. Sander, A. K. Singh, and A. Jantsch.
Verification of design decisions in ForSyDe.
In Proceedings of the 1st International Conference on Hardware -
Software Codesign and System Synthesis (CODES+ISSS), Newport Beach,
California, USA, October 2003.
[ bib |
DOI ]
design flow, verification
|
|
[2]
|
I. Sander, A. Jantsch, and Z. Lu.
Development and application of design transformations in ForSyDe.
IEE Proceedings - Computers & Digital Techniques,
5:313--320, September 2003.
Special Issue - Best of DATE '03.
[ bib |
DOI ]
design flow, refinement
|
|
[3]
|
A. Jantsch.
Modeling Embedded Systems and SoCs - Concurrency and Time in
Models of Computation.
Systems on Silicon. Morgan Kaufmann Publishers, June 2003.
[ bib |
www: ]
modeling
|
|
[4]
|
I. Sander.
System Modeling and Design Refinement in ForSyDe.
PhD thesis, Royal Institute of Technology, Stockholm, Sweden, April
2003.
[ bib |
.pdf ]
design flow, modeling, refinement, synthesis
|
|
[5]
|
I. Sander, A. Jantsch, and Z. Lu.
Development and application of design transformations in ForSyDe.
In Design, Automation and Test in Europe Conference (DATE
2003), pages 364--369, Munich, Germany, March 2003.
[ bib |
DOI ]
design flow, refinement
|
|
[1]
|
Z. Lu, I. Sander, and A. Jantsch.
A case study of hardware and software synthesis in ForSyDe.
In Proceedings of the 15th International Symposium on System
Synthesis, pages 86--91, Kyoto, Japan, October 2002.
[ bib |
DOI ]
design flow, synthesis
|
|
[2]
|
I. Sander and A. Jantsch.
Transformation based communication and clock domain refinement for
system design.
In 39th Design Automation Conference (DAC 2002), pages
281--286, New Orleans, USA, June 2002.
[ bib |
DOI ]
design flow, refinement
|
|
[1]
|
A. Jantsch, I. Sander, and W. Wu.
The usage of stochastic processes in embedded system specifications.
In Proceedings of the Ninth International Symposium on
Hardware/Software Codesign, pages 5--10, Copenhagen, Denmark, April 2001.
[ bib |
DOI ]
modeling
|
|
[1]
|
W. Wu, I. Sander, and A. Jantsch.
Transformational system design based on a formal computational model
and skeletons.
In Forum on Design Languages 2000, pages 321--328,
Tübingen, Germany, September 2000.
[ bib |
.pdf ]
design flow, refinement
|
|
[2]
|
A. Jantsch and I. Sander.
On the roles of functions and objects in system specification.
In Proceedings of the International Workshop on
Hardware/Software Codesign, pages 8--12, San Diego, CA, USA, 2000.
[ bib |
DOI ]
modeling
|
|
[1]
|
I. Sander and A. Jantsch.
System synthesis utilizing a layered functional model.
In Proceedings Seventh International Workshop on
Hardware/Software Codesign, pages 136--140, Rome, Italy, May 1999. ACM
Press.
[ bib |
DOI ]
design flow, synthesis
|
|
[2]
|
I. Sander and A. Jantsch.
System synthesis based on a formal computational model and skeletons.
In Proceedings IEEE Workshop on VLSI'99, pages 32--39,
Orlando, Florida, USA, April 1999. IEEE Computer Society.
[ bib |
DOI ]
design flow, synthesis
|
|
[3]
|
I. Sander and A. Jantsch.
Formal system design based on the synchrony hypothesis, functional
models, and skeletons.
In Proceedings of the 12th international conference on VLSI
Design, pages 318--323, Goa, India, January 1999. IEEE Computer Society.
[ bib |
DOI ]
design flow, modeling
|