We are happy to annouce the newer releases of IDeSyDe and ForSyDe IO. These newest releases enables you to solve DSE scenarios where the applications are modelled as SDF graphs and the platform contains FPGA elements which can host actors synthetized as ASICs. Naturally, this happens at the system-level, which means that the IDeSyDe makes mapping judgments based on number estimates and not on actual synthesis results. On the other hand, this has the advantage that you can use the DSE approach of this latest release with estimates of performance, in earlier stages of your design process.